[ACCEPTED]-Unsigned logic, vector and addition - How?-vhdl
In brief, you can add the
ieee.numeric_std package to your 33 architecture (
library ieee; use ieee.numeric_std.all;) and then do the addition 32 using:
Output <= std_logic_vector(unsigned(Output) + 1);
to convert your std_logic_vector to 31 an unsigned vector, increment it, and finally 30 convert the result back to an std_logic_vector.
Note 29 that if
Output is an output port, this won't work 28 because you can't access the value of an 27 output port within the same block. If that 26 is the case, you need to add a new signal 25 and then assign
Output from that signal, outside 24 your process.
If you do need to add a signal, it 23 might be simpler to make that signal a different 22 type than
std_logic_vector. For example, you could use an 21 integer or the
unsigned type above. For example:
architecture foo of bar is signal Output_int : integer range 0 to (2**Output'length)-1; begin PR: process(clk, resetn) begin if resetn='0' then Output_int <= 0; elsif clk'event and clk='1' then Output_int <= Output_int + 1; end if; end process; Output <= std_logic_vector(to_unsigned(Output_int, Output'length)); end foo;
Output_int is 20 declared with a range of valid values so 19 that tools will be able to determine both 18 the size of the integer as well as the range 17 of valid values for simulation.
In the declaration 16 of
Output'length is the width of the
Output vector (as an 15 integer), and the "**" operator is used 14 for exponentiation, so the expression means 13 "all unsigned integers that can be expressed 12 with as many bits as Output has".
For example, for 11 an
Output defined as
std_logic_vector(31 downto 0),
Output'length is 32. 232-1 is the highest 10 value that can be expressed with an unsigned 9 32-bit integer. Thus, in the example case, the 8
range 0 to (2**Output'length)-1 resolves to the range 0...4294967295 (232=4294967296), i.e. the 7 full unsigned range that can be expressed 6 with 32 bits.
Note that you'll need to add 5 any wrapping logic manually: VHDL simulators 4 will produce an error when you've reached 3 the maximum value and try to increment by 2 one, even if the synthesized logic will 1 cleanly wrap around to 0.
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